/* $Id: adc.h,v 1.18 2009/02/09 03:53:42 jagadish Exp $ */
/* $Id: adc.h,v 1.18 2009/02/09 03:53:42 jagadish Exp $ */
#include <p18cxxx.h>
#include <pconfig.h>


#ifndef __ADC_H
#define __ADC_H

/* PIC18 A/D conversion peripheral library. */

/* storage class of library routine parameters; pre-built with auto;
 * do not change unless you rebuild the libraries with the new storage class */ 

#define PARAM_SCLASS auto

/* ***** interrupt enable / disable */
#define ADC_INT_ENABLE()     {PIR1bits.ADIF = 0; INTCONbits.PEIE = 1;PIE1bits.ADIE = 1; }  
#define ADC_INT_DISABLE()    {PIE1bits.ADIE=0;}

//-----------------------------------------------------------
#if	defined (ADC_V1) || defined (ADC_V2) || defined (ADC_V3) || defined (ADC_V4) ||\
    defined (ADC_V5) || defined (ADC_V6) || defined (ADC_V8) || defined (ADC_V9) ||\
	defined (ADC_V10) || defined (ADC_V11) || defined (ADC_V12)
/* ***** clock source ***** */
#ifdef USE_OR_MASKS
#define ADC_FOSC_2       0b00000000 // A/D clock source Fosc/2
#define ADC_FOSC_4       0b01000000 // A/D clock source Fosc/4
#define ADC_FOSC_8       0b00010000 // A/D clock source Fosc/8
#define ADC_FOSC_16      0b01010000 // A/D clock source Fosc/16
#define ADC_FOSC_32      0b00100000 // A/D clock source Fosc/32
#define ADC_FOSC_64      0b01100000 // A/D clock source Fosc/64
#define ADC_FOSC_RC      0b01110000 // A/D clock source Internal RC OSC
#define ADC_FOSC_MASK	 (~ADC_FOSC_RC)		
/* ***** acquisition time ***** */
#define ADC_0_TAD        0b00000000
#define ADC_2_TAD        0b00000010
#define ADC_4_TAD        0b00000100
#define ADC_6_TAD        0b00000110
#define ADC_8_TAD        0b00001000
#define ADC_12_TAD       0b00001010
#define ADC_16_TAD       0b00001100
#define ADC_20_TAD       0b00001110
#define ADC_TAD_MASK	(~ADC_20_TAD)		
/********interrupt enable********/
#define ADC_INT_ON       0b10000000
#define ADC_INT_OFF      0b00000000
#define ADC_INT_MASK     ~ADC_INT_ON
//-------------------------------------------------
#else // USE_OR_MASKS
#define ADC_FOSC_2       0b10001111 // A/D clock source Fosc/2
#define ADC_FOSC_4       0b11001111 // A/D clock source Fosc/4
#define ADC_FOSC_8       0b10011111 // A/D clock source Fosc/8
#define ADC_FOSC_16      0b11011111 // A/D clock source Fosc/16
#define ADC_FOSC_32      0b10101111 // A/D clock source Fosc/32
#define ADC_FOSC_64      0b11101111 // A/D clock source Fosc/64
#define ADC_FOSC_RC      0b11111111 // A/D clock source Internal RC OSC
/* ***** acquisition time ***** */
#define ADC_0_TAD        0b11110001
#define ADC_2_TAD        0b11110011
#define ADC_4_TAD        0b11110101
#define ADC_6_TAD        0b11110111
#define ADC_8_TAD        0b11111001
#define ADC_12_TAD       0b11111011
#define ADC_16_TAD       0b11111101
#define ADC_20_TAD       0b11111111
/********interrupt enable********/
#define ADC_INT_ON       0b11111111
#define ADC_INT_OFF      0b01111111
#endif // USE_OR_MASKS

#endif

#if defined (ADC_V2) || defined (ADC_V3) || defined (ADC_V4) || defined (ADC_V5) ||\
    defined (ADC_V6) || defined (ADC_V8) || defined (ADC_V9) || defined (ADC_V11)||\
	defined (ADC_V12)
/* ***** voltage reference ***** */
#ifdef USE_OR_MASKS
#define ADC_REF_VDD_VREFMINUS   	0b00000010 // ADC voltage source VREF+ = VDD and VREF- = ext. source at VREF-
#define ADC_REF_VREFPLUS_VREFMINUS  0b00000011 // ADC voltage source VREF+ = ext. source at VREF+ and VREF- = ext. source at VREF-
#define ADC_REF_VREFPLUS_VSS		0b00000001 // ADC voltage source VREF+ = ext. source at VREF+ and VREF- = VSS
#define	ADC_REF_VDD_VSS  		    0b00000000 // ADC voltage source VREF+ = VDD and VREF- = VSS
#define ADC_REF_MASK	            (~ADC_REF_VREFPLUS_VREFMINUS)		
#else // USE_OR_MASKS			
#define ADC_REF_VDD_VREFMINUS   	0b11111110 // ADC voltage source VREF+ = VDD and VREF- = ext. source at VREF-
#define ADC_REF_VREFPLUS_VREFMINUS  0b11111111 // ADC voltage source VREF+ = ext. source at VREF+ and VREF- = ext. source at VREF-
#define ADC_REF_VREFPLUS_VSS		0b11111101 // ADC voltage source VREF+ = ext. source at VREF+ and VREF- = VSS
#define	ADC_REF_VDD_VSS  			0b11111100 // ADC voltage source VREF+ = VDD and VREF- = VSS
#endif // USE_OR_MASKS
#endif	

#ifdef	USE_OR_MASKS
/* ***** result justification ***** */
#define ADC_RIGHT_JUST   0b10000000 // Right justify A/D result
#define ADC_LEFT_JUST    0b00000000 // Left justify A/D result
#define ADC_RESULT_MASK	 (~ADC_RIGHT_JUST)
//------------------------------------------------------------
#else // USE_OR_MASKS
/* ***** result justification ***** */
#define ADC_RIGHT_JUST   0b11111111 // Right justify A/D result
#define ADC_LEFT_JUST    0b01111111 // Left justify A/D result
#endif // USE_OR_MASKS

//--------------------------------------------------------------
#if defined (ADC_V1)
#ifdef	USE_OR_MASKS
#define ADC_8ANA_0REF    0b00000000	// VREF+=VDD VREF-=VSS all analog channels   (8/0)
#define ADC_7ANA_1REF    0b00000001	// AN3=VREF+  all analog channels except AN3 (7/1)
#define ADC_5ANA_0REF    0b00000010 // VREF+=VDD VREF-=VSS  (5/0)
#define ADC_4ANA_1REF    0b00000011 // AN3=VREF+      (4/1)
#define ADC_3ANA_0REF    0b00000100 // VREF+=VDD VREF-=VSS  (3/0)
#define ADC_2ANA_1REF    0b00000101 // AN3=VREF+         (2/1)
#define ADC_0ANA_0REF    0b00000111 // ALL DIGITAL I/O      (0/0)
#define ADC_6ANA_2REF    0b00001000 // AN3=VREF+ AN2=VREF-  (6/2)
#define ADC_6ANA_0REF    0b00001001 // VREF+=VDD VREF-=VSS  (6/0)
#define ADC_5ANA_1REF    0b00001010 // AN3=VREF+ VREF-=VSS  (5/1)
#define ADC_4ANA_2REF    0b00001011 // AN3=VREF+ AN2=VREF-  (4/2)
#define ADC_3ANA_2REF    0b00001100 // AN3=VREF+ AN2=VREF-  (3/2)
#define ADC_2ANA_2REF    0b00001101 // AN3=VREF+ AN2=VREF-  (2/2)
#define ADC_1ANA_0REF    0b00001110 // AN0 is analog input  (1/0)
#define ADC_1ANA_2REF    0b00001111 // AN3=VREF+ AN2=VREF- AN0=A (1/2)
#define ADC_CONFIG_MASK	 (~ADC_1ANA_2REF)
//-----------------------------------------------------------------------------------
#else // USE_OR_MASKS
#define ADC_8ANA_0REF    0b11110000	// VREF+=VDD VREF-=VSS all analog channels   (8/0)
#define ADC_7ANA_1REF    0b11110001	// AN3=VREF+  all analog channels except AN3 (7/1)
#define ADC_5ANA_0REF    0b11110010 // VREF+=VDD VREF-=VSS  (5/0)
#define ADC_4ANA_1REF    0b11110011 // AN3=VREF+      (4/1)
#define ADC_3ANA_0REF    0b11110100 // VREF+=VDD VREF-=VSS  (3/0)
#define ADC_2ANA_1REF    0b11110101 // AN3=VREF+         (2/1)
#define ADC_0ANA_0REF    0b11110111 // ALL DIGITAL I/O      (0/0)
#define ADC_6ANA_2REF    0b11111000 // AN3=VREF+ AN2=VREF-  (6/2)
#define ADC_6ANA_0REF    0b11111001 // VREF+=VDD VREF-=VSS  (6/0)
#define ADC_5ANA_1REF    0b11111010 // AN3=VREF+ VREF-=VSS  (5/1)
#define ADC_4ANA_2REF    0b11111011 // AN3=VREF+ AN2=VREF-  (4/2)
#define ADC_3ANA_2REF    0b11111100 // AN3=VREF+ AN2=VREF-  (3/2)
#define ADC_2ANA_2REF    0b11111101 // AN3=VREF+ AN2=VREF-  (2/2)
#define ADC_1ANA_0REF    0b11111110 // AN0 is analog input  (1/0)
#define ADC_1ANA_2REF    0b11111111 // AN3=VREF+ AN2=VREF- AN0=A (1/2)
#endif // USE_OR_MASKS
//------------------------------------------------------------------
#elif defined (ADC_V2)
#ifdef USE_OR_MASKS
#define ADC_0ANA   0b00001111 // All digital
#define ADC_1ANA   0b00001110 // analog: AN0      digital: AN1->15
#define ADC_2ANA   0b00001101 // analog: AN0->1   digital: AN2->15
#define ADC_3ANA   0b00001100 // analog: AN0->2   digital: AN3->15
#define ADC_4ANA   0b00001011 // analog: AN0->3   digital: AN4->15
#define ADC_5ANA   0b00001010 // analog: AN0->4   digital: AN5->15
#define ADC_6ANA   0b00001001 // analog: AN0->5   digital: AN6->15
#define ADC_7ANA   0b00001000 // analog: AN0->6   digital: AN7->15
#define ADC_8ANA   0b00000111 // analog: AN0->7   digital: AN8->15
#define ADC_9ANA   0b00000110 // analog: AN0->8   digital: AN9->15
#define ADC_10ANA  0b00000101 // analog: AN0->9   digital: AN10->15
#define ADC_11ANA  0b00000100 // analog: AN0->10  digital: AN11->15
#define ADC_12ANA  0b00000011 // analog: AN0->11  digital: AN12->15
#define ADC_13ANA  0b00000010 // analog: AN0->12  digital: AN13->15
#define ADC_14ANA  0b00000001 // analog: AN0->13  digital: AN14->15
#define ADC_15ANA  0b00000000 // All analog
#define ADC_CONFIG_MASK  (~ADC_0ANA)
//------------------------------------------------------------------
#else // USE_OR_MASKS
#define ADC_0ANA   0b11111111 // All digital
#define ADC_1ANA   0b11111110 // analog: AN0      digital: AN1->15
#define ADC_2ANA   0b11111101 // analog: AN0->1   digital: AN2->15
#define ADC_3ANA   0b11111100 // analog: AN0->2   digital: AN3->15
#define ADC_4ANA   0b11111011 // analog: AN0->3   digital: AN4->15
#define ADC_5ANA   0b11111010 // analog: AN0->4   digital: AN5->15
#define ADC_6ANA   0b11111001 // analog: AN0->5   digital: AN6->15
#define ADC_7ANA   0b11111000 // analog: AN0->6   digital: AN7->15
#define ADC_8ANA   0b11110111 // analog: AN0->7   digital: AN8->15
#define ADC_9ANA   0b11110110 // analog: AN0->8   digital: AN9->15
#define ADC_10ANA  0b11110101 // analog: AN0->9   digital: AN10->15
#define ADC_11ANA  0b11110100 // analog: AN0->10  digital: AN11->15
#define ADC_12ANA  0b11110011 // analog: AN0->11  digital: AN12->15
#define ADC_13ANA  0b11110010 // analog: AN0->12  digital: AN13->15
#define ADC_14ANA  0b11110001 // analog: AN0->13  digital: AN14->15
#define ADC_15ANA  0b11110000 // All analog
#endif // USE_OR_MASKS
//----------------------------------------------------------------
#elif defined (ADC_V3)
#define ADC_0ANA   0b11111111 		// All digital
#define ADC_1ANA   0b11111110	 	// analog: AN0
#define ADC_2ANA   0b11111100 		// analog: AN0,AN1
#define ADC_3ANA   0b11111000 		// analog: AN0,AN1,AN2
#define ADC_4ANA   0b11110000 		// analog: AN0,AN1,AN2,AN3
#define ADC_5ANA   0b11100000 		// analog: AN0,AN1,AN2,AN3,AN4
#define ADC_6ANA   0b11000000 		// analog: AN0,AN1,AN2,AN3,AN4,AN5
#define ADC_7ANA   0b10000000 		// analog: AN0,AN1,AN2,AN3,AN4,AN5,AN6
//----------------------------------------------------------------
#elif defined (ADC_V4)
#define ADC_0ANA   0b00000000 		// All digital
#define ADC_1ANA   0b00000001	 	// analog: AN0
#define ADC_2ANA   0b00000011 		// analog: AN0,AN1
#define ADC_3ANA   0b00000111 		// analog: AN0,AN1,AN2
#define ADC_4ANA   0b00001111 		// analog: AN0,AN1,AN2,AN3
//----------------------------------------------------------------
#elif defined (ADC_V5) || defined (ADC_V6) || defined (ADC_V12) 
#define ADC_0ANA      0b00001111 // All digital
#define ADC_1ANA      0b00001110 // analog: AN0      digital: AN1->15
#define ADC_2ANA      0b00001101 // analog: AN0->1   digital: AN2->15
#define ADC_3ANA      0b00001100 // analog: AN0->2   digital: AN3->15
#define ADC_4ANA      0b00001011 // analog: AN0->3   digital: AN4->15
#define ADC_5ANA      0b00001010 // analog: AN0->4   digital: AN5->15
#define ADC_6ANA      0b00001001 // analog: AN0->5   digital: AN6->15
#define ADC_7ANA      0b00001000 // analog: AN0->6   digital: AN7->15
#define ADC_8ANA      0b00000111 // analog: AN0->7   digital: AN8->15
#define ADC_9ANA      0b00000110 // analog: AN0->8   digital: AN9->15
#define ADC_10ANA     0b00000101 // analog: AN0->9   digital: AN10->15
#define ADC_11ANA     0b00000100 // analog: AN0->10  digital: AN11->15
#define ADC_12ANA     0b00000011 // analog: AN0->11  digital: AN12->15
#define ADC_13ANA     0b00000010 // analog: AN0->12  digital: AN13->15
#define ADC_14ANA     0b00000001 // analog: AN0->13  digital: AN14->15
#define ADC_15ANA  	  0b00000000 // All analog
//-----------------------------------------------------------------
#elif defined (ADC_V8)
#define ADC_0ANA      0b0000000000000000 		// All digital
#define ADC_1ANA      0b0000000000000001	 	// analog: AN0
#define ADC_2ANA      0b0000000000000011 		// analog: AN0-AN1
#define ADC_3ANA      0b0000000000000111 		// analog: AN0-AN2
#define ADC_4ANA      0b0000000000001111 		// analog: AN0-AN3
#define ADC_5ANA      0b0000000000011111		// analog: AN0-AN4
#define ADC_6ANA      0b0000000000111111	 	// analog: AN0-AN5
#define ADC_7ANA      0b0000000001111111 		// analog: AN0-AN6
#define ADC_8ANA      0b0000000011111111 		// analog: AN0-AN7
#define ADC_9ANA      0b0000000111111111 		// analog: AN0-AN8
#define ADC_10ANA     0b0000001111111111 		// analog: AN0-An9
#define ADC_11ANA     0b0000011111111111	 	// analog: AN0-AN10
#define ADC_12ANA     0b0000111111111111 		// analog: AN0-AN11
#define ADC_13ANA     0b0001111111111111 		// analog: AN0-AN12
//-----------------------------------------------------------------
#elif defined (ADC_V9)
#define ADC_0ANA      0b1111111111111111 		// All digital
#define ADC_1ANA      0b1111111111111110	 	// analog: AN0
#define ADC_2ANA      0b1111111111111100 		// analog: AN0-AN1
#define ADC_3ANA      0b1111111111111000 		// analog: AN0-AN2
#define ADC_4ANA      0b1111111111110000 		// analog: AN0-AN3
#define ADC_5ANA      0b1111111111100000		// analog: AN0-AN4
#define ADC_6ANA      0b1111111111000000	 	// analog: AN0-AN5
#define ADC_7ANA      0b1111111110000000 		// analog: AN0-AN6
#define ADC_8ANA      0b1111111100000000 		// analog: AN0-AN7
#define ADC_9ANA      0b1111111000000000 		// analog: AN0-AN8
#define ADC_10ANA     0b1111110000000000 		// analog: AN0-An9
#define ADC_11ANA     0b1111100000000000	 	// analog: AN0-AN10
#define ADC_12ANA     0b1111000000000000 		// analog: AN0-AN11
#define ADC_13ANA     0b1110000000000000 		// analog: AN0-AN12
#define ADC_14ANA     0b1100000000000000	 	// analog: AN0-AN13
#define ADC_15ANA     0b1000000000000000 		// analog: AN0-AN14
#define ADC_16ANA     0b0000000000000000 		// analog: AN0-AN15
//----------------------------------------------------------------
#elif defined (ADC_V11)
#define ADC_0ANA      0b0001111111111111 		// All digital
#define ADC_1ANA      0b0001111111111110	 	// analog: AN0
#define ADC_2ANA      0b0001111111111100 		// analog: AN0-AN1
#define ADC_3ANA      0b0001111111111000 		// analog: AN0-AN2
#define ADC_4ANA      0b0001111111110000 		// analog: AN0-AN3
#define ADC_5ANA      0b0001111111100000		// analog: AN0-AN4
#define ADC_6ANA      0b0001111111000000	 	// analog: AN0-AN5
#define ADC_7ANA      0b0001111110000000 		// analog: AN0-AN6
#define ADC_8ANA      0b0001111100000000 		// analog: AN0-AN7
#define ADC_9ANA      0b0001111000000000 		// analog: AN0-AN8
#define ADC_10ANA     0b0001110000000000 		// analog: AN0-An9
#define ADC_11ANA     0b0001100000000000	 	// analog: AN0-AN10
#define ADC_12ANA     0b0001000000000000 		// analog: AN0-AN11
#define ADC_13ANA     0b0000000000000000 		// analog: AN0-AN12
/********Band Gap selection*********/
#define ADC_VBG_ON    0b1000000000000000      //VBG output of Band Gap module is enabled
#define ADC_VBG_OFF   0b0000000000000000      //VBG output of Band Gap module is disabled  
#define ADC_VBG2_ON   0b0100000000000000      //VBG/2 output of Band Gap module is enabled  
#define ADC_VBG2_OFF  0b0000000000000000      //VBG/2 output of Band Gap module is disabled  
//----------------------------------------------------------------
#endif

#if defined (ADC_V7) || defined (ADC_V7_1)
#ifdef USE_OR_MASKS
/* ***** A/D conversion type ****** */
#define	ADC_CONV_CONTINUOUS			0b00001000
#define	ADC_CONV_SINGLE_SHOT		0b00000000
#define ADC_CONV_TYPE_MASK			(~ADC_CONV_CONTINUOUS)
/* ***** A/D conversion mode ****** */
#define	ADC_MODE_MULTI_CH			0b00000100
#define	ADC_MODE_SINGLE_CH			0b00000000
#define ADC_MODE_MASK				(~ADC_MODE_MULTI_CH)
/* ***** A/D conversion sequence select ****** */
#define	ADC_CONV_SEQ_SEQM1			0b00000000
#define	ADC_CONV_SEQ_SEQM2			0b00000001
#define	ADC_CONV_SEQ_STNM1			0b00000010
#define	ADC_CONV_SEQ_STNM2			0b00000011
#define	ADC_CONV_SEQ_SCM1			0b00000000
#define	ADC_CONV_SEQ_SCM2			0b00000001
#define	ADC_CONV_SEQ_SCM3			0b00000010
#define	ADC_CONV_SEQ_SCM4			0b00000011
#define ADC_CONV_SEQ_MASK			(~ADC_CONV_SEQ_STNM2)
/* ***** A/D Vref selection ****** */
#define	ADC_REF_VDD_VREFMINUS		0b10000000
#define	ADC_REF_VREFPLUS_VSS		0b01000000
#define	ADC_REF_VREFPLUS_VREFMINUS	0b11000000
#define	ADC_REF_VDD_VSS				0b00000000
#define ADC_REF_MASK	            (~ADC_REF_VREFPLUS_VREFMINUS)
/* ***** A/D FIFO buffer control  ****** */
#define	ADC_FIFO_EN					0b00100000
#define	ADC_FIFO_DIS				0b00000000
#define ADC_FIFO_MASK				(~ADC_FIFO_EN)
/* ***** A/D Buffer depth interrupt control ****** */
#define	INT_EACH_WR_BUF				0b00000000
#define	INT_2_4_WR_BUF				0b01000000
#define	INT_4_WR_BUF				0b10000000
#define	INT_MASK				    (0b00111111)
/* ***** A/D trigger source ****** */
#define	ADC_TRIG_EXT_INT0			0b00000001
#define	ADC_TRIG_TMR_5				0b00000010
#define	ADC_TRIG_INP_CAP			0b00000100
#define	ADC_TRIG_CCP2_COM			0b00001000	
#define	ADC_TRIG_PCPWM				0b00010000
#define ADC_TRIG_MASK				(0b11100000) 
/* ***** A/D acquisition time ***** */
#define	ADC_0_TAD					0b00000000
#define	ADC_2_TAD					0b00001000
#define	ADC_4_TAD					0b00010000
#define	ADC_6_TAD					0b00011000
#define	ADC_8_TAD					0b00100000
#define	ADC_10_TAD					0b00101000
#define	ADC_12_TAD					0b00110000
#define	ADC_16_TAD					0b00111000
#define	ADC_20_TAD					0b01000000
#define	ADC_24_TAD					0b01001000
#define	ADC_28_TAD					0b01010000
#define	ADC_32_TAD					0b01011000
#define	ADC_36_TAD					0b01100000
#define	ADC_40_TAD					0b01101000
#define	ADC_48_TAD					0b01110000
#define	ADC_64_TAD					0b01111000
#define ADC_TAD_MASK				(~ADC_64_TAD)
/********interrupt enable********/
#define ADC_INT_ON                  0b00100000
#define ADC_INT_OFF                 0b00000000
#define ADC_INT_MASK                ~ADC_INT_ON

/* ***** A/D clock source ***** */
#define ADC_FOSC_2      		 	0b00000000 	// A/D clock source Fosc/2
#define ADC_FOSC_4      			0b00000100 	// A/D clock source Fosc/4
#define ADC_FRC_4        			0b00000011 	// A/D clock source FRC/4
#define ADC_FOSC_8       			0b00000001 	// A/D clock source Fosc/8
#define ADC_FOSC_16      			0b00000101 	// A/D clock source Fosc/16
#define ADC_FOSC_32      			0b00000010 	// A/D clock source Fosc/32
#define ADC_FOSC_64      			0b00000110 	// A/D clock source Fosc/64
#define ADC_FOSC_RC      			0b00000111 	// A/D clock source Internal RC OSC
#define ADC_FOSC_MASK				(~ADC_FOSC_RC)
//-----------------------------------------------------------------------------
#else 
/* ***** A/D conversion type ****** */
#define	ADC_CONV_CONTINUOUS			0b11111111
#define	ADC_CONV_SINGLE_SHOT		0b11110111
/* ***** A/D conversion mode ****** */
#define	ADC_MODE_MULTI_CH			0b11111111
#define	ADC_MODE_SINGLE_CH			0b11111011
/* ***** A/D conversion sequence select ****** */
#define	ADC_CONV_SEQ_SEQM1			0b11111100
#define	ADC_CONV_SEQ_SEQM2			0b11111101
#define	ADC_CONV_SEQ_STNM1			0b11111110
#define	ADC_CONV_SEQ_STNM2			0b11111111
#define	ADC_CONV_SEQ_SCM1			0b11111100
#define	ADC_CONV_SEQ_SCM2			0b11111101
#define	ADC_CONV_SEQ_SCM3			0b11111110
#define	ADC_CONV_SEQ_SCM4			0b11111111
/* ***** A/D Vref selection ****** */
#define	ADC_REF_VDD_VREFMINUS		0b10111111
#define	ADC_REF_VREFPLUS_VSS		0b01111111
#define	ADC_REF_VREFPLUS_VREFMINUS	0b11111111
#define	ADC_REF_VDD_VSS				0b00111111
/* ***** A/D FIFO buffer control  ****** */
#define	ADC_FIFO_EN					0b11111111
#define	ADC_FIFO_DIS				0b11011111
/* ***** A/D Buffer depth interrupt control ****** */
#define	INT_EACH_WR_BUF				0b00111111
#define	INT_2_4_WR_BUF				0b01111111
#define	INT_4_WR_BUF				0b10111111
/* ***** A/D trigger source ****** */
#define	ADC_TRIG_EXT_INT0			0b11100001
#define	ADC_TRIG_TMR_5				0b11100010
#define	ADC_TRIG_INP_CAP			0b11100100
#define	ADC_TRIG_CCP2_COM			0b11101000	
#define	ADC_TRIG_PCPWM				0b11110000
/* ***** A/D acquisition time ***** */
#define	ADC_0_TAD					0b10000111
#define	ADC_2_TAD					0b10001111
#define	ADC_4_TAD					0b10010111
#define	ADC_6_TAD					0b10011111
#define	ADC_8_TAD					0b10100111
#define	ADC_10_TAD					0b10101111
#define	ADC_12_TAD					0b10110111
#define	ADC_16_TAD					0b10111111
#define	ADC_20_TAD					0b11000111
#define	ADC_24_TAD					0b11001111
#define	ADC_28_TAD					0b11010111
#define	ADC_32_TAD					0b11011111
#define	ADC_36_TAD					0b11100111
#define	ADC_40_TAD					0b11101111
#define	ADC_48_TAD					0b11110111
#define	ADC_64_TAD					0b11111111
/********interrupt enable********/
#define ADC_INT_ON       			0b11111111
#define ADC_INT_OFF      			0b11011111
/* ***** A/D clock source ***** */
#define ADC_FOSC_2      		 	0b11111000 	// A/D clock source Fosc/2
#define ADC_FOSC_4      			0b11111100 	// A/D clock source Fosc/4
#define ADC_FRC_4        			0b11111011 	// A/D clock source FRC/4
#define ADC_FOSC_8       			0b11111001 	// A/D clock source Fosc/8
#define ADC_FOSC_16      			0b11111101 	// A/D clock source Fosc/16
#define ADC_FOSC_32      			0b11111010 	// A/D clock source Fosc/32
#define ADC_FOSC_64      			0b11111110 	// A/D clock source Fosc/64
#define ADC_FOSC_RC      			0b11111111 	// A/D clock source Internal RC OSC
#endif
#endif // Version specific declarations


#if defined (ADC_V11)
#ifdef USE_OR_MASKS
/********channel selection**********/
#define ADC_CH0          0b00000000  // Channel 0
#define ADC_CH1          0b00001000  // Channel 1
#define ADC_CH2          0b00010000  // Channel 2
#define ADC_CH3          0b00011000  // Channel 3
#define ADC_CH4          0b00100000  // Channel 4
#define ADC_CH5          0b00101000  // Channel 5
#define ADC_CH6          0b00110000  // Channel 6
#define ADC_CH7          0b00111000  // Channel 7
#define ADC_CH8          0b01000000  // Channel 8
#define ADC_CH9          0b01001000  // Channel 9
#define ADC_CH10         0b01010000  // Channel 10
#define ADC_CH11         0b01011000  // Channel  11
#define ADC_CH12         0b01100000  // Channel 12
#define ADC_CH_CTMU      0b01101000  // All analog inputs are off - CTMU
#define ADC_CH_VDDCORE   0b01110000  // VDDCORE Channel
#define ADC_CH_VBG       0b01111000  // Voltage Band gap channel
#define ADC_CH_MASK		(~0b01111000)
#else 
/* ***** channel selection ***** */
#define ADC_CH0          0b10000111  // Channel 0
#define ADC_CH1          0b10001111  // Channel 1
#define ADC_CH2          0b10010111  // Channel 2
#define ADC_CH3          0b10011111  // Channel 3
#define ADC_CH4          0b10100111  // Channel 4
#define ADC_CH5          0b10101111  // Channel 5
#define ADC_CH6          0b10110111  // Channel 6
#define ADC_CH7          0b10111111  // Channel 7
#define ADC_CH8          0b11000111  // Channel 8
#define ADC_CH9          0b11001111  // Channel 9
#define ADC_CH10         0b11010111  // Channel 10
#define ADC_CH11         0b11011111  // Channel 11
#define ADC_CH12         0b11100111  // Channel 12
#define ADC_CH_CTMU      0b11101111  // All analog inputs are off
#define ADC_CH_VDDCORE   0b11110111  // VDDCORE Channel
#define ADC_CH_VBG       0b11111111  // Voltage Band gap channel
#endif
#else

#ifdef USE_OR_MASKS
/* ***** channel selection ***** */
#define ADC_CH0          0b00000000  // Channel 0
#define ADC_CH1          0b00001000  // Channel 1
#define ADC_CH2          0b00010000  // Channel 2
#define ADC_CH3          0b00011000  // Channel 3
#define ADC_CH4          0b00100000  // Channel 4
#define ADC_CH5          0b00101000  // Channel 5
#define ADC_CH6          0b00110000  // Channel 6
#define ADC_CH7          0b00111000  // Channel 7
#define ADC_CH8          0b01000000  // Channel 8
#define ADC_CH9          0b01001000  // Channel 9
#define ADC_CH10         0b01010000  // Channel 10
#define ADC_CH11         0b01011000  // Channel  11
#define ADC_CH12         0b01100000  // Channel 12
#define ADC_CH13         0b01101000  // Channel 13
#define ADC_CH14         0b01110000  // Channel 14
#define ADC_CH15         0b01111000  // Channel 15
#define ADC_CH_MASK		(~ADC_CH15)
//------------------------------------------------
#else 
/* ***** channel selection ***** */
#define ADC_CH0          0b10000111  // Channel 0
#define ADC_CH1          0b10001111  // Channel 1
#define ADC_CH2          0b10010111  // Channel 2
#define ADC_CH3          0b10011111  // Channel 3
#define ADC_CH4          0b10100111  // Channel 4
#define ADC_CH5          0b10101111  // Channel 5
#define ADC_CH6          0b10110111  // Channel 6
#define ADC_CH7          0b10111111  // Channel 7
#define ADC_CH8          0b11000111  // Channel 8
#define ADC_CH9          0b11001111  // Channel 9
#define ADC_CH10         0b11010111  // Channel 10
#define ADC_CH11         0b11011111  // Channel 11
#define ADC_CH12         0b11100111  // Channel 12
#define ADC_CH13         0b11101111  // Channel 13
#define ADC_CH14         0b11110111  // Channel 14
#define ADC_CH15         0b11111111  // Channel 15
#endif
#endif

#if defined (ADC_V10)
#ifdef USE_OR_MASKS
/* ***** channel selection ***** */
//Channels AN0, AN1, AN2, AN12 ------ unused
#define ADC_CH3          0b00011000  // Channel 3
#define ADC_CH4          0b00100000  // Channel 4
#define ADC_CH5          0b00101000  // Channel 5
#define ADC_CH6          0b00110000  // Channel 6
#define ADC_CH7          0b00111000  // Channel 7
#define ADC_CH8          0b01000000  // Channel 8
#define ADC_CH9          0b01001000  // Channel 9
#define ADC_CH10         0b01010000  // Channel 10
#define ADC_CH11         0b01011000  // Channel  11

#define TEMP_REF_BANDGAP 0b01101000  // Temperature reference from BandGap
#define DAC1			 0b01110000  // DAC1
#define FVR1			 0b01111000  // FVR1
#define ADC_CH_MASK		(~ADC_CH15)
/* ***** Positive Voltage Reference Configuration bits ***** */
#define ADC_REF_VDD_VDD			0b00000000 // ADC voltage source VREF+ = AVDD
#define ADC_REF_VDD_VREFPLUS	0b00000100 // ADC voltage source VREF+ = ext. source at VREF+
#define ADC_REF_VDD_FVREF		0b00001000 // ADC voltage source VREF+ = FVREF+
//#define	ADC_REF_RESERVED  		0b00001100 // Reserved
/* ***** Negative Voltage Reference Configuration bits ***** */
#define ADC_REF_VDD_VSS		    0b00000000 // ADC voltage source VREF- = AVSS
#define ADC_REF_VDD_VREFMINUS	0b00000001 // ADC voltage source VREF- = ext. source at VREF-
//#define	ADC_REF_RESERVED  		           0b00000010 // Reserved
//#define	ADC_REF_RESERVED  		           0b00000011 // Reserved
//------------------------------------------------
#else //AND MASK
/* ***** channel selection ***** */
//Channels AN0, AN1, AN2, AN12 ------ unused
#define ADC_CH3          0b10011111  // Channel 3
#define ADC_CH4          0b10100111  // Channel 4
#define ADC_CH5          0b10101111  // Channel 5
#define ADC_CH6          0b10110111  // Channel 6
#define ADC_CH7          0b10111111  // Channel 7
#define ADC_CH8          0b11000111  // Channel 8
#define ADC_CH9          0b11001111  // Channel 9
#define ADC_CH10         0b11010111  // Channel 10
#define ADC_CH11         0b11011111  // Channel 11

#define TEMP_REF_BANDGAP         0b11101111  // Temperature reference from BandGap
#define DAC1			         0b11110111  // DAC1
#define FVR1			         0b11111111  // FVR1
/* ***** Positive Voltage Reference Configuration bits ***** */
#define ADC_REF_VDD_VDD			0b11111001 // ADC voltage source VREF+ = AVDD
#define ADC_REF_VDD_VREFPLUS 	0b11111011 // ADC voltage source VREF+ = ext. source at VREF+
#define ADC_REF_VDD_FVREF		0b11111101 // ADC voltage source VREF+ = FVREF+
//#define	ADC_REF_RESERVED  		0b11111111 // Reserved
/* ***** Negative Voltage Reference Configuration bits ***** */
#define ADC_REF_VDD_VSS			0b11111100 // ADC voltage source VREF- = AVSS
#define ADC_REF_VDD_VREFMINUS	0b11111101 // ADC voltage source VREF- = ext. source at VREF-
//#define	ADC_REF_RESERVED  		0b11111110 // Reserved
//#define	ADC_REF_RESERVED  		0b11111111 // Reserved
#endif
#endif
//--------------------------------------------------------------------------//
#if defined (ADC_V12)
#ifdef USE_OR_MASKS
#define ADC_TRIG_CTMU           0b10000000 //Special trigger from the CTMU
#define ADC_TRIG_CCP2           0b00000000 //Special trigger from CCP2
#define ADC_TRIG_MASK           (~ADC_TRIG_CTMU)
#else
#define ADC_TRIG_CTMU           0b11111111 //Special trigger from the CTMU
#define ADC_TRIG_CCP2           0b01111111 //Special trigger from CCP2
#endif
#endif

/* Stores the result of an A/D conversion. */
union ADCResult
{
	int lr;
 	char br[2];
};

/* BusyADC
 * Check status of A/D conversion; returns 1 if busy converting; 0 otherwise
 */
char BusyADC (void);

/* ConvertADC
 * Start an A/D conversion
 */
void ConvertADC (void);


/* Read ADC data
 */
int ReadADC(void);
void CloseADC (void);

/* openADC()****
*/
#if defined (ADC_V1) || defined (ADC_V2)

void OpenADC (PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned char );

#elif defined (ADC_V3) || defined (ADC_V4) || defined (ADC_V5) || defined (ADC_V6) ||\
      defined (ADC_V7) || defined (ADC_V7_1)|| defined (ADC_V12)

void OpenADC (PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned char );

#elif defined (ADC_V8) || defined (ADC_V9) 

void OpenADC (PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned int );

#elif defined (ADC_V10)

void OpenADC (PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned int );
			  
#elif defined (ADC_V11)

void OpenADC (PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned char ,
              PARAM_SCLASS unsigned int );
			  			  

#endif

/* SetChanADC
 * Set A/D to specified channel
 */
#if defined (ADC_V1) || defined (ADC_V2) || defined (ADC_V3) ||\
    defined (ADC_V4) || defined ( ADC_V5 ) || defined ( ADC_V6 )||\
	defined ( ADC_V8 ) || defined ( ADC_V9) || defined ( ADC_V10)||\
	defined ( ADC_V11) || defined (ADC_V12)
void SetChanADC(unsigned char );
#endif

/* SetChanADC
 * Starts and ADC Conversion
 */ 
void SelChanConvADC(PARAM_SCLASS unsigned char );

#if defined (ADC_V4)
#define ADC_SEVT_ENABLE()    {ADCON0bits.SEVTEN = 1; }  
#define ADC_SEVT_DISABLE()   {ADCON0bits.SEVTEN = 0;}
#endif
//**********************************/
#if defined (ADC_V6) || defined (ADC_V12)
#define	ADC_CALIB()	    {ADCON0bits.ADCAL = 1;}
#define	ADC_NO_CALIB()	{ADCON0  &= 0b01111111;	}

#elif defined (ADC_V9)
#define	ADC_CALIB()	    {WDTCONbits.DEVCFG = 0;ADCON1bits.ADCAL = 1;}
#define ADC_NO_CALIB()	{WDTCONbits.DEVCFG = 0;ADCON1&= 0b10111111;}

#elif defined (ADC_V11)
#define	ADC_CALIB()	    {ADCON1bits.ADCAL = 1;}
#define ADC_NO_CALIB()	{ADCON1&= 0b10111111;}

#endif

//---------------------------------/
#if defined (ADC_V7) || defined (ADC_V7_1)
/* ***** A/D channel from Gruop A ***** */
#define ADC_CH_GRA_SEL_AN0   0
#define ADC_CH_GRA_SEL_AN4   4

/* ***** A/D channel from Gruop B ***** */
#define ADC_CH_GRB_SEL_AN1   1

/* ***** A/D channel from Gruop C ***** */
#define ADC_CH_GRC_SEL_AN2   2

/* ***** A/D channel from Gruop D ***** */
#define ADC_CH_GRD_SEL_AN3   3

#define ADC_CH_GRA_AN0()	{ANSEL0 |= 0b00000001;ADCHS |=  0b00000011;ADCHS &=  0b11111100;}
#define ADC_CH_GRA_AN4()	{ANSEL0 |= 0b00010000;ADCHS |=  0b00000011;ADCHS &=  0b11111101;}
#define ADC_CH_GRB_AN1()	{ANSEL0 |= 0b00000010;ADCHS |=  0b00110000;ADCHS &=  0b11001111;}
#define ADC_CH_GRC_AN2()	{ANSEL0 |= 0b00000100;ADCHS |=  0b00001100;ADCHS &=  0b11110011;}
#define ADC_CH_GRD_AN3()	{ANSEL0 |= 0b00001000;ADCHS |=  0b11000000;ADCHS &=  0b00111111;}

#endif

#if defined (ADC_V7)

#define ADC_CH_GRB_SEL_AN5   5
#define ADC_CH_GRC_SEL_AN6   6
#define ADC_CH_GRD_SEL_AN7   7
#define ADC_CH_GRA_SEL_AN8   8

/* ***** A/D channel from Gruop B ***** */	
#define ADC_CH_GRB_AN5()	{ANSEL0 |= 0b00100000;ADCHS |=  0b00110000;ADCHS &=  0b11011111;}

/* ***** A/D channel from Gruop C ***** */
#define ADC_CH_GRC_AN6()	{ANSEL0 |= 0b01000000;ADCHS |=  0b00001100;ADCHS &=  0b11110111;}

/* ***** A/D channel from Gruop D ***** */				
#define ADC_CH_GRD_AN7()	{ANSEL0 |= 0b10000000;ADCHS |=  0b11000000;ADCHS &=  0b01111111;}

/* ***** A/D channel from Gruop A ***** */										
#define ADC_CH_GRA_AN8()	{ANSEL1 |= 0b00000001;ADCHS  |= 0b00000011;ADCHS &=  0b11111110;}

/* ***** All channel Digital ***** */
#define ALL_CH_DIGITAL()	{ANSEL0 = 0x0;ANSEL1 = 0x0;}
/**********************************/
#endif
/*Macros for backward compatibility*/ 

#if defined (ADC_V8)

#define ADC_CHAN0   0b1111111111111110  // AN0
#define ADC_CHAN1   0b1111111111111101  // AN1
#define ADC_CHAN2   0b1111111111111011  // AN2
#define ADC_CHAN3   0b1111111111110111  // AN3
#define ADC_CHAN4   0b1111111111101111  // AN4
#define ADC_CHAN5   0b1111111111011111  // AN5
#define ADC_CHAN6   0b1111111110111111  // AN6
#define ADC_CHAN7   0b1111111101111111  // AN7
#define ADC_CHAN8   0b1111111011111111  // AN8
#define ADC_CHAN9   0b1111110111111111  // AN9
#define ADC_CHAN10  0b1111101111111111  // AN10
#define ADC_CHAN11  0b1111011111111111  // AN11
#define ADC_CHAN12  0b1110111111111111  // AN12
#define ADC_CHAN13  0b1101111111111111  // AN13
#define ADC_CHAN14  0b1011111111111111  // AN14
#define ADC_CHAN15  0b0111111111111111  // AN15

#endif

#if defined ( ADC_V2 ) || defined (ADC_V3) || defined (ADC_V4 ) ||\
    defined ( ADC_V5 ) || defined ( ADC_V6 ) || defined (ADC_V7) ||\
	defined (ADC_V7_1) || defined ( ADC_V8 ) || defined (ADC_V9) ||\
	defined (ADC_V11) || defined (ADC_V12)
#define ADC_VREFPLUS_VDD	ADC_REF_VDD_VREFMINUS      // VREF+ = AVDD
#define ADC_VREFPLUS_EXT	ADC_REF_VREFPLUS_VREFMINUS // VREF+ = external
#define ADC_VREFMINUS_VSS	ADC_REF_VREFPLUS_VSS       // VREF- = AVSS
#define ADC_VREFMINUS_EXT	ADC_REF_VREFPLUS_VREFMINUS // VREF- = external

#elif defined (ADC_V10)
#define ADC_VREFPLUS_VDD	ADC_REF_VDD_VDD      // VREF+ = AVDD
#define ADC_VREFPLUS_EXT	ADC_REF_VDD_VREFPLUS // VREF+ = external
#define ADC_VREFMINUS_VSS	ADC_REF_VDD_VSS       // VREF- = AVSS
#define ADC_VREFMINUS_EXT	ADC_REF_VDD_VREFMINUS // VREF- = external

#endif

#endif
